Testing and Recon guration of VLSI Linear Arrays ?

Achieving fault-tolerance through incorporation of redundancy and recon-guration is quite common. In this paper we study the fault-tolerance of linear arrays of N processors with k bypass links whose maximum length is g. We consider both arrays with bidirectional links and unidirectional links. We rst consider the problem of testing whether a set of n faulty processors is catastrophic, i.e., precludes reconnguration. We provide new testing algorithms which improve and generalize known testing algorithms. For bidirectional arrays we provide an O(kn) time testing algorithm and for unidirectional arrays we provide an O(n) time algorithm for the case k = 1, and an O(kn log k) time algorithm, for the case k > 1. When the fault pattern is not catastrophic we study the problem of nd-ing an optimal reconnguration of the array. We consider optimality with respect to two parameters: the size of the reconngured array and the number of redundant links to activate. Considering optimality with respect to the size of the reconngured array, we prove that the problem is NP-hard in the strong sense if the bypass links are bidirectional, while it can be solved in O(kng) time if the bypass links are unidirectional. Considering optimality with respect to the number of bypass links to activate, we prove that the problem can be solved in O(kn) time if the bypass links are bidirectional, and in O(kng) time if the bypass links are unidirectional.